Computer Science and Information Technology
GATE CSE area:computing-and-data PYQs
Build your understanding with focused practice from past exam papers.
Questions 21–30 of 159. Imported answers require independent review unless marked reviewed.
Question 57
Open questionCS2NAT2 marksNeeds review
A non-pipelined instruction execution unit that operates at 1.6 GHz clock takes an average of 5 clock cycles to complete the execution of an instruction. To improve the performance, the system was pipelined with a goal of achieving an average throughput of one instruction per clock cycle. However, it could operate only at 1.2 GHz due to pipeline overheads. While executing a program in the pipelined design, 30% of instructions encountered a stall of 2 cycles due to pipeline hazards. The speed-up obtained by the pipelined design over the non-pipelined one for this program is __________. (rounded off to two decimal places)
Note: 1G=10⁹
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Open questionCS2NAT2 marksNeeds review
Consider a new TCP connection between a sender and a receiver. The receiver advertised window is constant at 48 KB, the maximum segment size (MSS) is 2 KB, and the slow start threshold for TCP congestion control is 16 KB. Assume that there are no timeouts or duplicate acknowledgements. The number of rounds of transmission required for the congestion control algorithm of the TCP connection to reach the congestion avoidance phase is __________. (answer in integer)
Note: 1K=2¹⁰
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Open questionCSNAT2 marksNeeds review
Consider a hard disk with a rotational speed of 1500 rpm. The time to move the read/write head from a track to its adjacent track is 1 millisecond. Initially, the head is on track 0. The number of sectors per track is 400. The sector size is 1024 bytes. It is necessary to transfer data from 10 randomly located sectors in each of the following tracks in the order: 5, 12 and 7. The total time for the data transfer (in milliseconds) from the hard disk is ________. (rounded off to one decimal place)
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Open questionCSNAT2 marksNeeds review
The EX stage of a pipelined processor performs the memory read operations for LOAD instructions, and the operations for the arithmetic and logic instructions. Let
denote the time taken by the EX stage to perform the operation for an instruction. For each instruction type, the values of
and
(the number of instructions of that type in a sequence of 100 instructions for a program P), are given in the table below. The duration of the pipeline clock cycle is 1 nanosecond. Assume that the latch time for the interstage buffers in the pipeline is negligible. Table (Instruction,
in nanoseconds,
): LOAD, 1.8, 15; MUL, 1.5, 10; IDIV, 2.5, 5; FADD, 1.7, 10; FSUB, 1.7, 5; FMUL, 2.8, 15; FDIV, 3.2, 5; All other instructions, Less than 1.0, 35. When program P is executed, the number of clock cycles for which the pipeline is stalled due to structural hazards in the EX stage is _____. (answer in integer)Log in to check the answer
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Open questionCS2NAT2 marksNeeds review
It is necessary to design a link-layer protocol between two hosts that are directly connected over a lossless link of length 300 kilometers. Assume that the link bandwidth is
bits per second and that the propagation delay in the link is 5 nanoseconds per meter. Every transmitted data byte is assigned a unique sequence number.Let
be the minimum number of bits needed for the sequence number field in the protocol header such thati. the sequence numbers do not wrap around before 60 seconds, and
ii. the maximum utilization of the link is achieved.
The value of
is ______. (answer in integer)Log in to check the answer
You can attempt this question now. Sign in to view the answer key, explanations and discussion.Log in to check answerQuestion 11
Open questionCSMCQ1 markNeeds review
Suppose a program is running on a non-pipelined single processor computer system. The computer is connected to an external device that can interrupt the processor asynchronously. The processor needs to execute the interrupt service routine (ISR) to serve this interrupt. The following steps (not necessarily in order) are taken by the processor when the interrupt arrives:
(i) The processor saves the content of the program counter.
(ii) The program counter is loaded with the start address of the ISR.
(iii) The processor finishes the present instruction.
Which ONE of the following is the CORRECT sequence of steps?
Your answerChoose one option.
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Open questionCSMCQ1 markNeeds review
Identify the ONE CORRECT matching between the OSI layers and their corresponding functionalities as shown.
OSI Layers | Functionalities |
|---|---|
(a) Network layer | (I) Packet routing |
(b) Transport layer | (II) Frame and error handling |
(c) Datalink layer | (III) Host to host communication |
Your answerChoose one option.
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You can attempt this question now. Sign in to view the answer key, explanations and discussion.Log in to check answerQuestion 16
Open questionCSMCQ1 markNeeds review
Consider the following statements:
(i) Address Resolution Protocol (AR) provides a mapping from an IP address to the corresponding hardware (link-layer) address.
(ii) A single TCP segment from a sender S to a receiver R cannot carry both data from S to R and acknowledgement for a segment from R to S.
Which ONE of the following is CORRECT?
Your answerChoose one option.
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You can attempt this question now. Sign in to view the answer key, explanations and discussion.Log in to check answerQuestion 17
Open questionCSMCQ1 markNeeds review
Consider the routing protocols given in List I and the names given in List II:
List I | List II
(i) Distance vector routing | (a) Bellman-Ford
(ii) Link state routing | (b) Dijkstra
For matching of items in List I with those in List II, which ONE of the following options is CORRECT?
Your answerChoose one option.
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Open questionCSMCQ1 markNeeds review
A machine receives an IPv4 datagram. The protocol field of the IPv4 header has the protocol number of a protocol X.
Which ONE of the following is NOT a possible candidate for X?
Your answerChoose one option.
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