Computer Science and Information Technology
GATE CSE area:computing-and-data PYQs
Build your understanding with focused practice from past exam papers.
Questions 71–80 of 159. Imported answers require independent review unless marked reviewed.
Question 65
Open questionCS1NAT2 marksNeeds review
Consider sending an IP datagram of size 1420 bytes (including 20 bytes of IP header) from a sender to a receiver over a path of two links with a router between them. The first link (sender to router) has an MTU (Maximum Transmission Unit) size of 542 bytes, while the second link (router to receiver) has an MTU size of 360 bytes. The number of fragments that would be delivered at the receiver is ________.
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Open questionCSMCQ1 markNeeds review
Suppose two hosts are connected by a point-to-point link and they are configured to use Stop-and-Wait protocol for reliable data transfer. Identify in which one of the following scenarios, the utilization of the link is the lowest.
Your answerChoose one option.
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Open questionCSMSQ1 markNeeds review
Which one or more of the following need to be saved on a context switch from one thread (T1) of a process to another thread (T2) of the same process?
Your answerSelect all correct options. You can choose more than one.
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Which of the following statements is/are INCORRECT about the OSPF (Open Shortest Path First) routing protocol used in the Internet?
Your answerSelect all correct options. You can choose more than one.
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Open questionCSNAT1 markNeeds review
Consider a 3-stage pipelined processor having a delay of 10 ns (nanoseconds), 20 ns, and 14 ns, for the first, second, and the third stages, respectively. Assume that there is no other delay and the processor does not suffer from any pipeline hazards. Also assume that one instruction is fetched every cycle.
The total execution time for executing 100 instructions on this processor is _____ ns.
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Open questionCSNAT1 markNeeds review
A keyboard connected to a computer is used at a rate of 1 keystroke per second. The computer system polls the keyboard every 10 ms (milli seconds) to check for a keystroke and consumes 100
s (micro seconds) for each poll. If it is determined after polling that a key has been pressed, the system consumes an additional 200
s to process the keystroke. Let
denote the fraction of a second spent in polling and processing a keystroke.In an alternative implementation, the system uses interrupts instead of polling. An interrupt is raised for every keystroke. It takes a total of 1 ms for serving an interrupt and processing a keystroke. Let
denote the fraction of a second spent in serving the interrupt and processing a keystroke.The ratio
is ______. (Rounded off to one decimal place)Log in to check the answer
You can attempt this question now. Sign in to view the answer key, explanations and discussion.Log in to check answerQuestion 41
Open questionCSMCQ2 marksNeeds review
Consider the given C-code and its corresponding assembly code, with a few operands U1–U4 being unknown. Some useful information as well as the semantics of each unique assembly instruction is annotated as inline comments in the code. The memory is byte-addressable.
//C-code ;assembly-code (; indicates comments)
;r1-r5 are 32-bit integer registers
;initialize r1=0, r2=10
;initialize r3, r4 with base address of a, b
int a[10], b[10], i; L01: jeq r1, r2, end ;if(r1==r2) goto end
// int is 32-bit L02: lw r5, 0(r4) ;r5 <- Memory[r4+0]
for (i=0; i<10; i++) L03: shl r5, r5, U1 ;r5 <- r5 << U1
a[i] = b[i] * 8; L04: sw r5, 0(r3) ;Memory[r3+0] <- r5
L05: add r3, r3, U2 ;r3 <- r3+U2
L06: add r4, r4, U3
L07: add r1, r1, 1
L08: jmp U4 ;goto U4
L09: end
Which one of the following options is a CORRECT replacement for operands in the position (U1, U2, U3, U4) in the above assembly code?
Your answerChoose one option.
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You can attempt this question now. Sign in to view the answer key, explanations and discussion.Log in to check answerQuestion 42
Open questionCSMCQ2 marksNeeds review
A 4 kilobyte (KB) byte-addressable memory is realized using four 1 KB memory blocks. Two input address lines (IA4 and IA3) are connected to the chip select (CS) port of these memory blocks through a decoder as shown in the figure. The remaining ten input address lines from IA11–IA0 are connected to the address port of these blocks. The chip select (CS) is active high.
The input memory address (IA11–IA0), in decimal, for the starting locations (Addr=0) of each block (indicated as X1, X2, X3, X4 in the figure are among the options given below. Which one of the following options is CORRECT?
Your answerChoose one option.
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Open questionCSMSQ2 marksNeeds review
Suppose you are asked to design a new reliable byte-stream transport protocol like TCP. This protocol, named myTCP, runs over a 100 Mbps network with Round Trip Time of 150 milliseconds and the maximum segment life of 2 minutes. Which of the following is/are valid lengths of the Sequence Number field in the myTCP header?
Your answerSelect all correct options. You can choose more than one.
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Open questionCSMSQ2 marksNeeds review
Suppose in a web browser, you click on the
www.gate-2023.in
URL. The browser cache is empty. The IP address for this URL is not cached in your local host, so a DNS lookup is triggered (by the local DNS server deployed on your local host) over the 3-tier DNS hierarchy in an iterative mode. No resource records are cached anywhere across all DNS servers. Let RTT denote the round trip time between your local host and DNS servers in the DNS hierarchy. The round trip time between the local host and the web server hosting www.gate-2023.in
is also equal to RTT. The HTML file associated with the URL is small enough to have negligible transmission time and negligible rendering time by your web browser, which references 10 equally small objects on the same web server. Which of the following statements is/are CORRECT about the minimum elapsed time between clicking on the URL and your browser fully rendering it?Your answerSelect all correct options. You can choose more than one.
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