Computer Science and Information Technology
GATE CSE branch:cs PYQs
Build your understanding with focused practice from past exam papers.
Questions 941–950 of 975. Imported answers require independent review unless marked reviewed.
Question 48
Open questionCSNAT2 marksNeeds review
If a random variable
has a Poisson distribution with mean 5, then the expectation
equals __________.Log in to check the answer
You can attempt this question now. Sign in to view the answer key, explanations and discussion.Log in to check answerQuestion 49
Open questionCSNAT2 marksNeeds review
Consider a RISC machine where each instruction is exactly 4 bytes long. Conditional and unconditional branch instructions use PC-relative addressing mode with Offset specified in bytes to the target location of the branch instruction. Further the Offset is always with respect to the address of the next instruction in the program sequence. Consider the following instruction sequence
Instr. No. | Instruction |
|---|---|
i | add R2, R3, R4 |
i+1 | sub R5, R6, R7 |
i+2 | cmp R1, R9, R10 |
i+3 | beq R1, Offset |
If the target of the branch instruction is i, then the decimal value of the Offset is __________.
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Open questionCSNAT2 marksNeeds review
In a B+ tree, if the search-key value is 8 bytes long, the block size is 512 bytes and the block pointer size is 2 bytes, then the maximum order of the B+ tree is __________.
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You can attempt this question now. Sign in to view the answer key, explanations and discussion.Log in to check answerQuestion 50
Open questionCSNAT2 marksNeeds review
Instruction execution in a processor is divided into 5 stages, Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Execute (EX), and Write Back (WB). These stages take 5, 4, 20, 10, and 3 nanoseconds (ns) respectively. A pipelined implementation of the processor requires buffering between each pair of consecutive stages with a delay of 2 ns. Two pipelined implementations of the processor are compiled:
(i) a naive pipeline implementation (NP) with 5 stages and
(ii) an efficient pipeline (EP) where the OF stage is divided into stages OF1 and OF2 with execution times of 12 ns and 8 ns respectively.
The speedup (correct to two decimal places) achieved by EP over NP in executing 20 independent instructions with no hazards is __________.
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Open questionCSNAT2 marksNeeds review
A message is made up entirely of characters from the set
. The table of probabilities for each of the characters is shown below.Character | Probability |
|---|---|
| 0.22 |
| 0.34 |
| 0.17 |
| 0.19 |
| 0.08 |
Total | 1.00 |
If a message of 100 characters over
is encoded using Huffman coding, then the expected length of the encoded message in bits is __________.Log in to check the answer
You can attempt this question now. Sign in to view the answer key, explanations and discussion.Log in to check answerQuestion 51
Open questionCSNAT2 marksNeeds review
Consider a 2-way set associative cache with 256 blocks and uses LRU replacement. Initially the cache is empty. Conflict misses are those misses which occur due to contention of multiple blocks for the same cache set. Compulsory misses occur due to first time access to the block. The following sequence of accesses to memory blocks
(0, 128, 256, 128, 0, 128, 256, 128, 1, 129, 257, 129, 1, 129, 257, 129)
is repeated 10 times. The number of conflict misses experienced by the cache is _________.
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Open questionCSNAT2 marksNeeds review
Consider the set of processes with arrival time (in milliseconds), CPU burst time (in milliseconds), and priority (0 is the highest priority) shown below. None of the processes have I/O burst time.
Process | Arrival Time | Burst Time | Priority |
|---|---|---|---|
| 0 | 11 | 2 |
| 5 | 28 | 0 |
| 12 | 2 | 3 |
| 2 | 10 | 1 |
| 9 | 16 | 4 |
The average waiting time (in milliseconds) of all the processes using preemptive priority scheduling algorithm is __________.
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Open questionCSNAT2 marksNeeds review
Consider the expression
. Let X be the minimum number of registers required by an optimal code generation (without any register spill) algorithm for a load/store architecture, in which (i) only load and store instructions can have memory operands and (ii) arithmetic instructions can have only register or immediate operands. The value of X is ________.Log in to check the answer
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Open questionCSNAT2 marksNeeds review
If the characteristic polynomial of a
matrix
over
(the set of real numbers) is
,
, and one eigenvalue of
is 2, then the largest among the absolute values of the eigenvalues of
is __________.Log in to check the answer
You can attempt this question now. Sign in to view the answer key, explanations and discussion.Log in to check answerQuestion 53
Open questionCSNAT2 marksNeeds review
Consider the following C program.
#include<stdio.h>
#include <string.h>
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