GATE CSE · 2017 · CS
Question 51: Computer Organization and Architecture
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Question 51
CSNAT2 marksNeeds review
Consider a 2-way set associative cache with 256 blocks and uses LRU replacement. Initially the cache is empty. Conflict misses are those misses which occur due to contention of multiple blocks for the same cache set. Compulsory misses occur due to first time access to the block. The following sequence of accesses to memory blocks
(0, 128, 256, 128, 0, 128, 256, 128, 1, 129, 257, 129, 1, 129, 257, 129)
is repeated 10 times. The number of conflict misses experienced by the cache is _________.
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2017CS
GATE CSE 2017 · Paper 1
Computer Science and Information Technology · Original paper archive
- Section
- Computer Science and Information Technology
- Question type
- Numerical answer (NAT)
- Marks
- 2 marks
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