GATE CSE concept:main-memory PYQs & Answers — Page 2

Questions 11–18 of 18. Imported answers require independent review unless marked reviewed.

A direct mapped cache memory of 1 MB has a block size of 256 bytes. The cache has an access time of 3 ns and a hit rate of 94%. During a cache miss, it takes 20 ns to bring the first word of a block from the main memory, while each subsequent word takes 5 ns. The word size is 64 bits. The average memory access time in ns (round off to 1 decimal place) is ________.

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A computer system with a word length of 32 bits has a 16 MB byte-addressable main memory and a 64 KB, 4-way set associative cache memory with a block size of 256 bytes. Consider the following for physical addresses represented in hexadecimal notation.

A1 = 0x42C8A4, A2 = 0x54688, A3 = 0x6A289C, A4 = 0x5E480

Which one of the following is TRUE?

Your answerChoose one option.

A1 and A4 are mapped to different cache sets.

A2 and A3 are mapped to the same cache set.

A3 and A4 are mapped to the same cache set.

A1 and A3 are mapped to the same cache set.

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Consider a page system that uses 1-level page table residing in main memory and a TLB for address translation. Each main memory access takes 100 ns and TLB lookup takes 20 ns. Each page transfer to/from the disk takes 500 ns. Assume that the TLB hit ratio is 95%, page fault rate is 10%. Assume that for 20% of the total page faults, a dirty page has to be written back to disk before the required page is read in from disk. TLB update time is negligible. The average memory access time in ns (round off to 1 decimal places) is ______.

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A certain processor uses a fully associative cache of size 16 kB. The cache block size is 16 bytes. Assume that the main memory is byte addressable and uses a 32-bit address. How many bits are required for the Tag and the Index fields respectively in the addresses generated by the processor?

Your answerChoose one option.

24 bits and 0 bits

28 bits and 4 bits

24 bits and 4 bits

28 bits and 0 bits

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A 32-bit wide main memory unit with a capacity of 1 GB is built using 256 M × 4-bit DRAM chips. The number of rows of memory cells in the DRAM chip is

. The time taken to perform one refresh operation is 50 nanoseconds. The refresh period is 2 milliseconds. The percentage (rounded to the closest integer) of the time available for performing the memory read/write operations in the main memory unit is ________.

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In a two-level cache system, the access times of

and

caches are 1 and 8 clock cycles, respectively. The miss penalty from the

cache to main memory is 18 clock cycles. The miss rate of

cache is twice that of

. The average memory access time (AMAT) of this cache system is 2 cycles. The miss rates of

and

respectively are:

Your answerChoose one option.

0.111 and 0.056

0.056 and 0.111

0.0892 and 0.1784

0.1784 and 0.0892

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The read access times and the hit ratios for different caches in a memory hierarchy are as given below.

Cache	Read access time (in nanoseconds)	Hit ratio
I-cache	2	0.8
D-cache	2	0.9
L2-cache	8	0.9

The read access time of main memory is 90 nanoseconds. Assume that the caches use the referred-word-first read policy and the write back policy. Assume that all the caches are direct mapped caches. Assume that the dirty bit is always 0 for all the blocks in the caches. In execution of a program, 60% of memory reads are for instruction fetch and 40% are for memory operand fetch. The average read access time in nanoseconds (up to 2 decimal places) is __________.

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Consider a machine with a byte addressable main memory of

bytes divided into blocks of size 32 bytes. Assume that a direct mapped cache having 512 cache lines is used with this machine. The size of the tag field in bits is __________.

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GATE CSE concept:main-memory PYQs

Question 21

Question 30

Question 53

Question 1

Question 23

Question 29

Question 45

Question 53