GATE CSE topic:computer-organization-and-architecture PYQs & Answers — Page 9 — Exam Papers

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topic:computer-organization-and-architecture

Questions 81–87 of 87. Imported answers require independent review unless marked reviewed.

Topic practice 87 questionsPage 9 of 9

In a two-level cache system, the access times of

and

caches are 1 and 8 clock cycles, respectively. The miss penalty from the

cache to main memory is 18 clock cycles. The miss rate of

cache is twice that of

. The average memory access time (AMAT) of this cache system is 2 cycles. The miss rates of

and

respectively are:

Your answerChoose one option.

A.

0.111 and 0.056

B.

0.056 and 0.111

C.

0.0892 and 0.1784

D.

0.1784 and 0.0892

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The read access times and the hit ratios for different caches in a memory hierarchy are as given below.

Cache	Read access time (in nanoseconds)	Hit ratio
I-cache	2	0.8
D-cache	2	0.9
L2-cache	8	0.9

The read access time of main memory is 90 nanoseconds. Assume that the caches use the referred-word-first read policy and the write back policy. Assume that all the caches are direct mapped caches. Assume that the dirty bit is always 0 for all the blocks in the caches. In execution of a program, 60% of memory reads are for instruction fetch and 40% are for memory operand fetch. The average read access time in nanoseconds (up to 2 decimal places) is __________.

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Consider a RISC machine where each instruction is exactly 4 bytes long. Conditional and unconditional branch instructions use PC-relative addressing mode with Offset specified in bytes to the target location of the branch instruction. Further the Offset is always with respect to the address of the next instruction in the program sequence. Consider the following instruction sequence

Instr. No.	Instruction
i	add R2, R3, R4
i+1	sub R5, R6, R7
i+2	cmp R1, R9, R10
i+3	beq R1, Offset

If the target of the branch instruction is i, then the decimal value of the Offset is __________.

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Instruction execution in a processor is divided into 5 stages, Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Execute (EX), and Write Back (WB). These stages take 5, 4, 20, 10, and 3 nanoseconds (ns) respectively. A pipelined implementation of the processor requires buffering between each pair of consecutive stages with a delay of 2 ns. Two pipelined implementations of the processor are compiled: (i) a naive pipeline implementation (NP) with 5 stages and (ii) an efficient pipeline (EP) where the OF stage is divided into stages OF1 and OF2 with execution times of 12 ns and 8 ns respectively.

The speedup (correct to two decimal places) achieved by EP over NP in executing 20 independent instructions with no hazards is __________.

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Consider a 2-way set associative cache with 256 blocks and uses LRU replacement. Initially the cache is empty. Conflict misses are those misses which occur due to contention of multiple blocks for the same cache set. Compulsory misses occur due to first time access to the block. The following sequence of accesses to memory blocks

(0, 128, 256, 128, 0, 128, 256, 128, 1, 129, 257, 129, 1, 129, 257, 129)

is repeated 10 times. The number of conflict misses experienced by the cache is _________.

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Consider a machine with a byte addressable main memory of

bytes divided into blocks of size 32 bytes. Assume that a direct mapped cache having 512 cache lines is used with this machine. The size of the tag field in bits is __________.

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A cache memory unit with capacity of

words and block size of

words is to be designed. If it is designed as a direct mapped cache, the length of the TAG field is 10 bits. If the cache unit is now designed as a 16-way set-associative cache, the length of the TAG field is ______ bits.

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