GATE CSE year:2017 PYQs & Answers — Page 11

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Questions 101–110 of 130. Imported answers require independent review unless marked reviewed.

Topic practice 130 questionsPage 11 of 13

Consider a 2-way set associative cache with 256 blocks and uses LRU replacement. Initially the cache is empty. Conflict misses are those misses which occur due to contention of multiple blocks for the same cache set. Compulsory misses occur due to first time access to the block. The following sequence of accesses to memory blocks

(0, 128, 256, 128, 0, 128, 256, 128, 1, 129, 257, 129, 1, 129, 257, 129)

is repeated 10 times. The number of conflict misses experienced by the cache is _________.

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Consider the set of processes with arrival time (in milliseconds), CPU burst time (in milliseconds), and priority (0 is the highest priority) shown below. None of the processes have I/O burst time.

Arrival Time	Burst Time	Priority
0	11	2
5	28	0
12	2	3
2	10	1
9	16	4

The average waiting time (in milliseconds) of all the processes using preemptive priority scheduling algorithm is __________.

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Consider the expression

. Let X be the minimum number of registers required by an optimal code generation (without any register spill) algorithm for a load/store architecture, in which (i) only load and store instructions can have memory operands and (ii) arithmetic instructions can have only register or immediate operands. The value of X is ________.

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If the characteristic polynomial of a

matrix

over

(the set of real numbers) is

, and one eigenvalue of

is 2, then the largest among the absolute values of the eigenvalues of

is __________.

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Consider the following C program.

#include<stdio.h> #include <string.h>

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Consider a machine with a byte addressable main memory of

bytes divided into blocks of size 32 bytes. Assume that a direct mapped cache having 512 cache lines is used with this machine. The size of the tag field in bits is __________.

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A cache memory unit with capacity of

words and block size of

words is to be designed. If it is designed as a direct mapped cache, the length of the TAG field is 10 bits. If the cache unit is now designed as a 16-way set-associative cache, the length of the TAG field is ______ bits.

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Consider the following C Program.

#include<stdio.h>

int main() {

int m = 10;

int n, n1;

n = ++m;

n1 = m++;

n--;

--n1;

n -= n1;

printf("%d", n);

return 0;

}

The output of the program is __________.

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The output of executing the following C program is ________.

#include<stdio.h>

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Consider the following C Program.

#include<stdio.h>

#include<string.h>

int main() {

char* c = "GATECSIT2017";

char* p = c;

printf("%d", (int)strlen(c+2[p]-6[p]-1));

return 0;

}

The output of the program is __________.

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GATE CSE year:2017 PYQs

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Question 55

Question 55