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Electronics and Communication Engineering

GATE ECE topic:sequential-circuits PYQs

Build your understanding with focused practice from past exam papers.

Questions 21–24 of 24. Imported answers require independent review unless marked reviewed.

Topic practice 24 questionsPage 3 of 3

Question 17

Open question
ECNAT1 markNeeds review
Consider the D-Latch shown in the figure, which is transparent when its clock input CK is high and has zero propagation delay. In the figure, the clock signal CLK1 has a 50% duty cycle and CLK2 is a one-fifth period delayed version of CLK1. The duty cycle at the output of the latch in percentage is
Diagram for Electronics and Communication Engineering question 17

.

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Question 43

Open question
ECNAT2 marksNeeds review
The state diagram of a finite state machine (FSM) designed to detect an overlapping sequence of three bits is shown in the figure. The FSM has an input ‘In’ and an output ‘Out’. The initial state of the FSM is S₀.
Diagram for Electronics and Communication Engineering question 43

If the input sequence is 10101101001101, starting with the left-most bit, then the number of times ‘Out’ will be 1 is ______

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Question 44

Open question
ECNAT2 marksNeeds review
A 4-bit shift register circuit configured for right-shift operation, i.e.

,

,

,

, is shown. If the present state of the shift register is

, the number of clock cycles required to reach the state

is ____________.
Diagram for Electronics and Communication Engineering question 44


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Question 46

Open question
ECMCQ2 marksNeeds review
A finite state machine (FSM) is implemented using the D flip-flops A and B, and logic gates, as shown in the figure below. The four possible states of the FSM are

and

.
Diagram for Electronics and Communication Engineering question 46

Assume that

is held at a constant logic level throughout the operation of the FSM. When the FSM is initialized to the state

and clocked, after a few clock cycles, it starts cycling through
Your answerChoose one option.

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