GATE ECE · 2017 · EC
Question 46: Sequential circuits
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Question 46
ECMCQ2 marksNeeds review
A finite state machine (FSM) is implemented using the D flip-flops A and B, and logic gates, as shown in the figure below. The four possible states of the FSM are
and
.
Assume that
is held at a constant logic level throughout the operation of the FSM. When the FSM is initialized to the state
and clocked, after a few clock cycles, it starts cycling throughYour answerChoose one option.
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2017EC
GATE ECE 2017 · Paper 1
Electronics and Communication Engineering · Original paper archive
- Section
- Electronics and Communication Engineering
- Question type
- Multiple choice (MCQ)
- Marks
- 2 marks
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