Computer Science and Information Technology
GATE CSE topic:computing PYQs
Build your understanding with focused practice from past exam papers.
Questions 641–650 of 975. Imported answers require independent review unless marked reviewed.
Question 51
Open questionCSNAT2 marksNeeds review
In a pushdown automaton
, a transition of the form
where
,
, and
, represents
.Consider the following pushdown automaton over the input alphabet
and stack alphabet
.
The number of strings of length 100 accepted by the above pushdown automaton is __________.
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Consider the following augmented grammar with
as the set of terminals.
Let
. The number of items in the set
is ____________.Log in to check the answer
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Consider the following matrix.
The largest eigenvalue of the above matrix is __________.
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Consider a Boolean function
such that
The number of literals in the minimal sum-of-products expression of
is ____________.Log in to check the answer
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A five-stage pipeline has stage delays of 150, 120, 150, 160 and 140 nanoseconds. The registers that are used between the pipeline stages have a delay of 5 nanoseconds each.
The total time to execute 100 independent instructions on this pipeline, assuming there are no pipeline stalls, is __________ nanoseconds.
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Consider a pipelined processor with 5 stages, Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MEM), and Write Back (WB). Each stage of the pipeline, except the EX stage, takes one cycle. Assume that the ID stage merely decodes the instruction and the register read is performed in the EX stage. The EX stage takes one cycle for ADD instruction and two cycles for MUL instruction. Ignore pipeline register latencies.
Consider the following sequence of 8 instructions:
ADD, MUL, ADD, MUL, ADD, MUL, ADD, MUL
Assume that every MUL instruction is data-dependent on the ADD instruction just before it and every ADD instruction (except the first ADD) is data-dependent on the MUL instruction just before it. The speedup is defined as follows:
The speedup achieved in executing the given instruction sequence on the pipelined processor (rounded to 2 decimal places) is ____________.
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A sender (
) transmits a signal, which can be one of the two kinds:
and
with probabilities 0.1 and 0.9 respectively, to a receiver (
).
In the graph below, the weight of edge
is the probability of receiving
when
is transmitted, where
. For example, the probability that the received signal is
given the transmitted signal was
, is 0.7.
If the received signal is
, the probability that the transmitted signal was
(rounded to 2 decimal places) is __________.Log in to check the answer
You can attempt this question now. Sign in to view the answer key, explanations and discussion.Log in to check answerQuestion 54
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Consider a network using the pure ALOHA medium access control protocol, where each frame is of length 1,000 bits. The channel transmission rate is 1 Mbps (=
bits per second). The aggregate number of transmissions across all the nodes (including new frame transmissions and retransmitted frames due to collisions) is modeled as a Poisson process with a rate of 1,000 frames per second. Throughput is defined as the average number of frames successfully transmitted per second. The throughput of the network (rounded to the nearest integer) is ____________.Log in to check the answer
You can attempt this question now. Sign in to view the answer key, explanations and discussion.Log in to check answerQuestion 55
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Consider the following instruction sequence where registers R1, R2 and R3 are general purpose and MEMORY[X] denotes the content at the memory location X.
Instruction | Semantics | Instruction Size (bytes) |
|---|---|---|
MOV R1, (500) | R1 ← MEMORY[500] | 4 |
MOV R2, (R3) | R2 ← MEMORY[R3] | 4 |
ADD R2, R1 | R2 ← R1+R2 | 2 |
MOV (R3), R2 | MEMORY[R3] ← R2 | 4 |
INC R3 | R3 ← R3+1 | 2 |
DEC R1 | R1 ← R1-1 | 2 |
BNZ 104 | Branch if not zero to the given absolute address | 2 |
HALT | Stop | 1 |
Assume that the content of the memory location 500 is 10, and the content of the register R3 is 300. The content of each of the memory locations from 300 to 3010 is 50. The instruction sequence starts from the memory location 100. All the numbers are in decimal format. Assume that the memory is byte addressable.
After the execution of the program, the content of memory location 3010 is __________.
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In a directed acyclic graph with a source vertex
, the quality-score of a directed path is defined to be the product of the weights of the edges on the path. Further, for a vertex
other than
, the quality-score of
is defined to be the maximum among the quality-scores of all the paths from
to
. The quality-score of
is assumed to be 1.
The sum of the quality-scores of all the vertices in the graph shown above is ____________.
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