GATE ECE topic:signals-and-systems PYQs & Answers — Page 68

Questions 671–680 of 715. Imported answers require independent review unless marked reviewed.

The state diagram of a finite state machine (FSM) designed to detect an overlapping sequence of three bits is shown in the figure. The FSM has an input ‘In’ and an output ‘Out’. The initial state of the FSM is S₀.

Diagram for Electronics and Communication Engineering question 43

If the input sequence is 10101101001101, starting with the left-most bit, then the number of times ‘Out’ will be 1 is ______

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A 4-bit shift register circuit configured for right-shift operation, i.e.

, is shown. If the present state of the shift register is

, the number of clock cycles required to reach the state

is ____________.

Diagram for Electronics and Communication Engineering question 44

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Figure I shows a 4-bit ripple carry adder realized using full adders and Figure II shows the circuit of a full-adder (FA). The propagation delay of the XOR, AND and OR gates in Figure II are 20 ns, 15 ns and 10 ns, respectively. Assume all the inputs to the 4-bit adder are initially reset to 0.

Diagram for Electronics and Communication Engineering question 44 (figure 2)

, the inputs to the 4-bit adder are changed to

and

. The output of the ripple carry adder will be stable at

(in ns) = ______

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The following FIVE instructions were executed on an 8085 microprocessor.

MVI A, 33H MVI B, 78H ADD B CMA ANI 32H

The Accumulator value immediately after the execution of the fifth instruction is

Your answerChoose one option.

00H

10H

11H

32H

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A programmable logic array (PLA) is shown in the figure. The Boolean function

implemented is

Diagram for Electronics and Communication Engineering question 45

Your answerChoose one option.

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A finite state machine (FSM) is implemented using the D flip-flops A and B, and logic gates, as shown in the figure below. The four possible states of the FSM are

and

Diagram for Electronics and Communication Engineering question 46

Assume that

is held at a constant logic level throughout the operation of the FSM. When the FSM is initialized to the state

and clocked, after a few clock cycles, it starts cycling through

Your answerChoose one option.

all of the four possible states if

three of the four possible states if

only two of the four possible states if

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A unity feedback control system is characterized by the open-loop transfer function

. The value of

for which the system oscillates at

is ________

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A linear time invariant (LTI) system with the transfer function

is connected in unity feedback configuration as shown in the figure.

Diagram for Electronics and Communication Engineering question 47

For the closed loop system shown, the root locus for

intersects the imaginary axis for

. The closed loop system is stable for

Your answerChoose one option.

no positive value of

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A second-order LTI system is described by the following state equations,

, where

and

are the two state variables and

denotes the input. The output

. The system is

Your answerChoose one option.

undamped (oscillatory)

underdamped

critically damped

overdamped

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Which one of the following options correctly describes the locations of the roots of the equation

on the complex plane?

Your answerChoose one option.

Four left half plane (LHP) roots

One right half plane (RHP) root, one LHP root and two roots on the imaginary axis

Two RHP roots and two LHP roots

All four roots are on the imaginary axis

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GATE ECE topic:signals-and-systems PYQs

Question 43

Question 44

Question 44

Question 45

Question 45

Question 46

Question 46

Question 47

Question 47

Question 48