GATE ECE · 2017 · EC
Question 44: Combinational circuits
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Question 44
ECNAT2 marksNeeds review
Figure I shows a 4-bit ripple carry adder realized using full adders and Figure II shows the circuit of a full-adder (FA). The propagation delay of the XOR, AND and OR gates in Figure II are 20 ns, 15 ns and 10 ns, respectively. Assume all the inputs to the 4-bit adder are initially reset to 0.
At
, the inputs to the 4-bit adder are changed to
,
and
. The output of the ripple carry adder will be stable at
(in ns) = ______Log in to check the answer
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2017EC
GATE ECE 2017 · Paper 2
Electronics and Communication Engineering · Original paper archive
- Section
- Electronics and Communication Engineering
- Question type
- Numerical answer (NAT)
- Marks
- 2 marks
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