GATE ECE 2017 Paper 2 — page 15

Questions 43–45 of 65. Imported answers require review unless explicitly marked reviewed.

The state diagram of a finite state machine (FSM) designed to detect an overlapping sequence of three bits is shown in the figure. The FSM has an input ‘In’ and an output ‘Out’. The initial state of the FSM is S₀.

Diagram for Electronics and Communication Engineering question 43

If the input sequence is 10101101001101, starting with the left-most bit, then the number of times ‘Out’ will be 1 is ______

You can attempt this question now. Sign in to view the answer key, explanations and discussion.Log in to check answer

Figure I shows a 4-bit ripple carry adder realized using full adders and Figure II shows the circuit of a full-adder (FA). The propagation delay of the XOR, AND and OR gates in Figure II are 20 ns, 15 ns and 10 ns, respectively. Assume all the inputs to the 4-bit adder are initially reset to 0.

Diagram for Electronics and Communication Engineering question 44

Diagram for Electronics and Communication Engineering question 44 (figure 2)

, the inputs to the 4-bit adder are changed to

and

. The output of the ripple carry adder will be stable at

(in ns) = ______

You can attempt this question now. Sign in to view the answer key, explanations and discussion.Log in to check answer

A programmable logic array (PLA) is shown in the figure. The Boolean function

implemented is

Diagram for Electronics and Communication Engineering question 45

Your answerChoose one option.

You can attempt this question now. Sign in to view the answer key, explanations and discussion.Log in to check answer

2017 · Paper 2

Question 43

Question 44

Question 45