GATE CSE topic:computer-organization-and-architecture PYQs & Answers — Page 4

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topic:computer-organization-and-architecture

Questions 31–40 of 87. Imported answers require independent review unless marked reviewed.

Topic practice 87 questionsPage 4 of 9

Consider two set-associative cache memory architectures: WB, which uses the write back policy, and WT, which uses the write through policy. Both of them use the LRU (Least Recently Used) block replacement policy. The cache memory is connected to the main memory. Which of the following statements is/are TRUE?

Your answerSelect all correct options. You can choose more than one.

A read miss in WB never evicts a dirty block

A read miss in WT never triggers a write back operation of a cache block to main memory

A write hit in WB can modify the value of the dirty bit of a cache block

A write miss in WT always writes the victim cache block to main memory before loading the missed block to the cache

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Consider a disk with the following specifications: rotation speed of 6000 RPM, average seek time of 5 milliseconds, 500 sectors/track, 512-byte sectors. A file has content stored in 3000 sectors located randomly on the disk. Assuming average rotational latency, the total time (in seconds, rounded off to 2 decimal places) to read the entire file from the disk is ________

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Consider a 512 GB hard disk with 32 storage surfaces. There are 4096 sectors per track and each sector holds 1024 bytes of data. The number of cylinders in the hard disk is ________

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The baseline execution time of a program on a 2 GHz single core machine is 100 nanoseconds (ns). The code corresponding to 90% of the execution time can be fully parallelized. The overhead for using an additional core is 10 ns when running on a multicore system. Assume that all cores in the multicore system run their share of the parallelized code for an equal amount of time.

The number of cores that minimize the execution time of the program is ________

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A given program has 25% load/store instructions. Suppose the ideal CPI (cycles per instruction) without any memory stalls is 2. The program exhibits 2% miss rate on instruction cache and 8% miss rate on data cache. The miss penalty is 100 cycles. The speedup (rounded off to two decimal places) achieved with a perfect cache (i.e., with NO data or instruction cache misses) is ________

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A processor with 16 general purpose registers uses a 32-bit instruction format. The instruction format consists of an opcode field, an addressing mode field, two register operand fields, and a 16-bit scalar field. If 8 addressing modes are to be supported, the maximum number of unique opcodes possible for every addressing mode is ________

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A non-pipelined instruction execution unit operating at 2 GHz takes an average of 6 cycles to execute an instruction of a program P. The unit is then redesigned to operate on a 5-stage pipeline at 2 GHz. Assume that the ideal throughput of the pipelined unit is 1 instruction per cycle. In the execution of program P, 20% instructions incur an average of 2 cycles stall due to data hazards and 20% instructions incur an average of 3 cycles stall due to control hazards. The speedup (rounded off to one decimal place) obtained by the pipelined design over the non-pipelined design is ________

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A processor uses a 32-bit instruction format and supports byte-addressable memory access. The ISA of the processor has 50 distinct instructions. The instructions are equally divided into two types, namely R-type and I-type, whose formats are shown below.

In the OPCODE, 1 bit is used to distinguish between I-type and R-type instructions and the remaining bits indicate the operation. The processor has 50 architectural registers, and all register fields in the instructions are of equal size.

Let

be the number of bits used to encode the UNUSED field,

be the number of bits used to encode the OPCODE field, and

be the number of bits used to encode the immediate value/address field. The value of

is ________

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Consider a 32-bit system with 4 KB page size and page table entries of size 4 bytes each. Assume 1 KB =

bytes. The OS uses a 2-level page table for memory management, with the page table containing an outer page directory and an inner page table. The OS allocates a page for the outer page directory upon process creation. The OS uses demand paging when allocating memory for the inner page table, i.e., a page of the inner page table is allocated only if it contains at least one valid page table entry.

An active process in this system accesses 200 unique pages during its execution, and none of the pages are swapped out to disk. After it completes the page accesses, let

denote the minimum and

denote the maximum number of pages across the two levels of the page table of the process.

The value of X+Y is ________

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Which one or more of the following need to be saved on a context switch from one thread (T1) of a process to another thread (T2) of the same process?

Your answerSelect all correct options. You can choose more than one.

Page table base register

Stack pointer

Program counter

General purpose registers

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GATE CSE topic:computer-organization-and-architecture PYQs

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Question 22